Modern integrated circuits (ICs) are fabricated on semiconductor wafers that are mass produced in fabrication sites. The fabrications sites (or “fabs”) employ various types of automatic equipment that must function to very exacting and carefully controlled operating parameters. FIG. 1 depicts some of the process steps that are carried out.
At the upper left region of FIG. 1, a sequence of wafers come into a so-called wafer track system 10. A chill plate 20 typically is used to stabilize the wafer temperature by about 0.2° C. to room temperature before the wafers enter a spin coater 30 where a film of polymer photoresist is placed on the upper surface of the wafer. In some processes, at step 30 an anti-reflection coating may first be deposited upon the upper wafer surface and the wafer then baked (e.g., step 40) and then placed in the spin coater 30 for deposition of photoresist. In some processes an additional top layer of anti-reflection film may also be added at step 30. At modern photolithography seeks to define smaller and smaller feature size using shorter wavelength light, ultraviolet reflectivity becomes a greater problem, and thus the use of anti-reflection layer(s).
Eventually the wafer is robotically passed to a bake plate 40 where the film of photoresist is hardened and excess solvents are driven out of the wafer with heat. A subsequent chill plate process 50 cools the wafers to a stabilized room temperature, after which the wafers are presented to an exposure tool 60 that typically includes stepper and scanner functions. At step 70, the wafers are subjected to a post-exposure bake (PEB), using a PEB bake plate, and then to a chill plate 80, that returns the wafers to a stabilized ambient room temperature. A developer module stage 90 typically follows, during which the latent lithographic image that was formed during the exposure tool stage 60 is now developed in the polymer film on the wafer upper surface. In a positive tone image, the portions of the photoresist exposed to light will become soluble and dissolve away in solution to expose desired regions of the wafer structure. A bake plate step 100 follows the dry and harden the wafer surface. An etcher step 110 then follows, and then a cassette of the thus-processed wafers is returned to a chill plate, e.g., step 20. Various of the steps or stages shown in FIG. 1 may be repeated for the same wafer dozens of time, depending upon the specifics of the processes involved.
The goal in any fab is to produce wafers with the smallest possible feature size, and with a high production yield exceeding 80%. Meeting this goal requires that contaminants in the fab are controlled and that production parameters are controlled to where a substantial number of the wafers fully meet specification.
Fabrication variations due to lithography have decreased in recent years, thanks in part to the use of shorter wavelength light sources during the exposure tool phase of wafer fabrication. While use of 248 nm laser light promotes small element definition during fabrication, the decreased intensity of such light sources increases system throughput, as longer exposure times are required. The user of such laser wavelengths reduces throughput for system 10 to perhaps 160 wafers per hour. As a result, substantial work in the prior art has been directed to improving photoresists, including development of amplified (or chemically catalyzed) photoresists. Such photoresists essentially permit one photon of light source energy to affect multiple molecules within the photoresist material, thus reducing system throughput time. One consequence of enhanced performance from exposure tool step 60 is that post-exposure bake step 70 becomes a substantial factor in achieving specification with respect to critical dimensions in defining wafer patterns. Generally speaking, the post-exposure bake step now represents from perhaps 50% to 60% of the error contributed by system 10 in achieving critical dimensions in wafer production. (Perhaps 25% of the remaining error is associated with developer module 90, and perhaps 15% from spin coater 30.)
The challenge in designing a PEB bake plate is to achieve high uniformity in the ability to achieve and maintain within specification a desired and reproducible PEB temperature over a given period of time. The design goal is made difficult by the fact the spin coater 30 typically can accommodate many different types of photoresists, each requiring a different PEB bake plate temperature and time regime. Users of system 10 want a PEB unit 70 that can be rapidly programmed to accommodate different thermal set points for different photoresists.
Achieving good thermal uniformity across a PEB bake plate that is perhaps 13″ (33 cm) in diameter has been a difficult challenge in the prior art. The PEB bake plate typically functions within an enclosure that can be exhausted by a vacuum system. The temperature uniformity across the face of a PEB bake plate should be within ±0.1° C., a specification that is often not met in industry. Difficult as this uniformity specification has been to meet, ideally uniformity across the bake plate face should preferably be within ±0.05° C., a goal that appears rather unattainable in the prior art.
FIG. 2A depicts a prior art bake plate 150 as may be used within a PEB module 70 and/or any or all of bake plate modules 40 and 100 in FIG. 1. Bake plate 150 includes a disk 160 of a thermally conductive material, typically aluminum, whose underside defines grooves or recesses 170 into which a coil of resistive wire 180 is inserted. A disk 190 of aluminum is then bonded to the underside of disk 160. An electrical power source Vs is coupled to each end of wire 180. Electrically current flowing through wire 180 generates heat, similarly to the operation of a kitchen toaster, and in this fashion bake plate 150 can be heated. A robotically controlled platform 200 is coupled to a plurality of lift pins 210 that can pass vertically through opening 220 in bake plate 160. A wafer 230 is robotically placed atop pins 210, and can be lowered to be in thermal contact with the upper surface of bake plate 150 by moving mechanism 200 downward. Non-unitary construction bake plates such as shown generically in FIG. 2A are manufactured by Watlow of Chicago, Ill.
Resistive wire heater 180 is essentially permanently enveloped between aluminum elements 160 and 190 during casting of the aluminum. Although thermal paste or adhesive (not shown) is used within cavities 170 to help bond with the heater wire, it is difficult to maintain a consistent thermal interface between portions of the wire and the interior of the cavities 170. In some regions the interface may be relative good but less good in other regions, perhaps due to inconsistency in the physical dimensions of the wire or grooves. Further, initial good thermal contact may deteriorate with time, with the result that long term stability and predictability of bake plate 160 is questionable.
FIG. 2B depicts a somewhat similar bake plate 250 of a type manufactured by Minco (a Minnesota company) and Joeun Technology (a Korean company). Bake plate 250 includes an aluminum disk 260 that has resistive thin film heater elements 270 encased within low thermal conductivity polyimide sheets 290. The heater elements generate heat when coupled to a voltage source Vs. Unfortunately bake plate 250 is laminated and is subject to delamination in use, e.g., sheets 290 can come loose from disk260, rendering the bake plate useless for a wafer fabrication application.
As noted, prior art bake plates such as shown in FIGS. 2A and 2B have a difficult time meeting the present ±0.1° C. design specification, let alone the future anticipated specification of ±0.05° C. Further, consistency and reproducibility of the thermal characteristics of such bake plates is needed, as is longer bake plate longevity.
The present invention provides an integrally formed bake plate with improved thermal characteristics, improved thermal consistency and reproducibility, and enhanced longevity.